Job Description
This role involves close collaboration with architecture, RTL, and software teams to enable early architecture exploration, virtual prototyping, performance analysis, and hardware-software co-design. The candidate should have strong expertise in SystemC, C/C++, embedded systems, simulation environments, and transaction-level modeling, with exposure to semiconductor or SoC development environments.
Key Responsibilities :
– Design, develop, and maintain SystemC/TLM models for system-level simulation and architectural exploration.
– Build accurate and reusable transaction-level models (TLM) to represent SoC components, subsystems, and communication interfaces.
– Collaborate with system architects, RTL designers, and software teams to define and model system behavior.
– Support virtual platform development for early software bring-up and validation.
– Perform performance modeling, profiling, analysis, and optimization of system-level models.
– Integrate SystemC models with simulation frameworks, virtual prototypes, and co-simulation environments.
– Validate models against architecture specifications, functional requirements, and RTL implementations.
– Debug and troubleshoot simulation/modeling issues and improve model fidelity and performance.
– Contribute to hardware-software co-verification and early-stage software development using virtual platforms.
– Develop and enhance models for interconnects, memory subsystems, peripherals, and protocol behavior.
– Participate in architecture reviews, design discussions, and technical problem solving.
– Support verification and test teams in model validation and regression activities.
– Create technical documentation for model architecture, interfaces, and validation results.
Required Skills & Qualifications :
– Bachelors or Masters degree in Electronics, Computer Engineering, Embedded Systems, or related field.
– 48+ years of hands-on experience in SystemC development and system-level modeling.
– Strong programming expertise in C and C++.
– Hands-on experience with SystemC and TLM (Transaction-Level Modeling).
– Strong understanding of computer architecture, SoC design, and embedded systems.
– Experience with simulation tools, debugging techniques, and model validation.
– Knowledge of hardware-software co-design methodologies.
– Experience working with system-level simulation and virtual prototype environments.
– Good understanding of modeling abstractions, timing concepts, and performance analysis.
– Familiarity with scripting using Python or Shell for automation is a plus.
Preferred Skills :
– Experience in semiconductor or SoC development environments.
– Exposure to virtual platforms and architectural simulators.
– Hands-on experience with hardware/software co-verification.
– Knowledge of standard interconnect protocols such as :
a. AXI
b. AMBA
c. AHB/APB
d. Cache and memory subsystem protocols
– Familiarity with RTL concepts and interaction between SystemC models and RTL simulations.
– Exposure to processor modeling, performance simulators, or virtual validation platforms is a plus.
– Experience with multi-core or heterogeneous system modeling is desirable.
Nice to Have :
– Experience with emulation/prototyping environments.
– Knowledge of ARM-based architectures and SoC subsystems.
– Exposure to UVM/verification concepts is an advantage.
– Familiarity with compiler/toolchain behavior for embedded software bring-up.
– Experience in low-power or performance optimization analysis is a plus.
Are you interested in this position?
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