Digital Design Engineer

Job Description

Job Description

We are seeking a Digital Design Engineer with a strong foundation in RTL development and system-level architecture to contribute to the design and verification of high-performance digital subsystems. This role focuses on the design of custom IP blocks, integration of third-party IP, and optimization of digital logic in complex SoC environments. Candidates must have direct experience working with FPGAs or ASICs in either silicon or emulation environments.

Responsibilities

• Design and implement synthesizable RTL for digital subsystems using Verilog/SystemVerilog.
• Collaborate with system architects to translate functional requirements into efficient hardware designs.
• Develop parameterized, reusable IPs with emphasis on timing closure, area, and power.
• Perform block-level and top-level simulations, and work closely with verification teams to enable thorough functional coverage.
• Conduct synthesis, static timing analysis (STA), linting, CDC checks, and logic equivalence checks.
• Interface with physical design teams to guide floorplanning, place-and-route, and integration constraints.
• Participate in design reviews and contribute to design methodology improvements.
• Integrate IP blocks and verify design interoperability in pre-silicon environments.

Required Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent discipline.
• 4+ years of hands-on experience in digital design for ASIC or FPGA platforms.
• Proficiency in RTL design with Verilog and SystemVerilog.
• Deep understanding of digital logic concepts including pipelining, clock domain crossing, finite state machines, and low-power design.
• Demonstrated experience with industry-standard EDA tools (Synopsys, Cadence, or Siemens/Mentor) for logic synthesis and STA.
• Experience with scripting languages (Python, Tcl, Perl) to support automation and flow customization.
• Prior work on bus protocols (AXI4, AHB, APB) and memory interface logic (DDR, LPDDR, SRAM) integration.
• Familiarity with scan insertion, DFT concepts, and constraints management for testability.

Are you interested in this position?

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