Digital Design Engineer

Job Description

Role Overview:
We are seeking a Digital Design Engineer with a strong background in RTL design for high-performance, low-power digital systems. The ideal candidate will contribute to the architecture, implementation, and verification of custom IP cores and SoC components for next-generation data processing and communication platforms.

Key Responsibilities:

• Architect and implement synthesizable RTL (SystemVerilog preferred) for custom IP blocks, including datapaths, control logic, and interface modules (AXI, AMBA, PCIe, etc.).
• Collaborate with system architects to define block-level micro-architecture based on performance, area, and power targets.
• Integrate IP into subsystem and top-level designs, ensuring timing closure and logical correctness.
• Perform pre-silicon verification using industry-standard simulation tools and methodologies (UVM, SystemVerilog Assertions).
• Drive synthesis, linting, CDC/RDC analysis, and participate in formal equivalence checking.
• Work closely with physical design, firmware, and validation teams to support design bring-up and debug.

Required Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• Minimum 3 years of hands-on experience in RTL design for ASIC or FPGA.
• Proven expertise in SystemVerilog and digital design principles (FSMs, pipelining, clock domain crossing).
• Strong familiarity with common on-chip protocols: AXI4, AHB, APB, SPI, I2C, PCIe.
• Experience with industry-standard EDA tools: Synopsys (Design Compiler, VCS), Cadence (Genus, Xcelium), or Siemens (Questa).
• Proficient in scripting languages (Python, TCL, Make) for design automation.
• Solid understanding of STA, timing constraints, and timing ECO processes.

Are you interested in this position?

Apply by clicking on the “Apply Now” button below!

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