Digital Design Engineer

Job Description

We are seeking a detail-oriented Digital Design Engineer with hands-on experience in advanced RTL design and verification for complex digital systems. This role demands a blend of deep technical expertise in FPGA and ASIC design flows, a knack for automation, and strong collaboration skills to drive innovative hardware solutions from concept to silicon.

Job Requirements:

• Proven experience designing complex digital circuits using Verilog/SystemVerilog or VHDL, with a portfolio that includes at least one full chip or subsystem tapeout.
• Deep understanding of FPGA architecture and hands-on experience with Xilinx or Intel FPGA toolchains, including timing closure and resource optimization.
• Skilled in writing synthesizable RTL code that meets stringent performance and area constraints, coupled with a strong grasp of low-power design techniques.
• Demonstrated ability to develop and debug comprehensive testbenches using UVM or equivalent methodologies, ensuring robust verification coverage at block and system levels.
• Experience working directly with ASIC physical design teams, understanding the flow from RTL to GDSII, and ability to interpret synthesis and place-and-route reports to improve design quality.
• Proficiency in scripting (Python, TCL, or Perl) to automate design flows, generate reports, or create custom verification environments.
• Solid foundation in digital signal processing (DSP) concepts and their implementation in hardware for real-time applications.
• Familiarity with high-speed interfaces (PCIe, DDR, USB, Ethernet) and ability to design controllers or bridges compliant with relevant standards.
• Aptitude for collaborative problem-solving within cross-functional teams involving firmware, hardware validation, and system architects.
• Passion for continuous learning and keeping up with emerging digital design tools, methodologies, and industry trends.

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